this document is a general product descr iption and is subject to change without notice. hynix electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 04 / oct .01 hynix semiconductor hy62 u f16404d series 25 6kx16bit full cmos sram document title 256k x16 bit 2.7 ~ 3.3v super low power fcmos slow sram revision history revision no history draft date remark 00 initial draft dec.20.2000 preliminary 01 changed logo mar.23.2001 preliminary 02 changed isb1 values jun.07.2001 preliminary 03 changed package size (6.1mm - > 6.0mm) aug.07.2001 preliminary 04 changed tchz,tohz,tbhz 30ns - > 20ns oct . 22 . 2001 final
hy62 uf16404d series rev. 04 / oct .01 2 preliminary descript ion the hy62uf16404 d is a high speed, super low power and 4mbit full cmos sram organized as 256k words by 16bits. the hy62uf1640 4d uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particularly well - suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1. 5 v. features fully static operation and tri - state output ttl compatible inputs and outputs battery backup - . 1. 5 v(min) data retention standard pin configuration - . 48 - ball fbga standby current(ua) product no. voltage (v) speed (ns) operation current /icc(ma) ll sl te mperature ( c ) hy62uf1640 4d - i 2.7~3.3 55/70 4 12 6 - 40~85 note 1. i : industrial 2. current value is max. pin connection block diagram pin description pin name pin fun c tion pin name pin fun c tion /cs chip select i/o1~i/o16 data input s /output s /we wri te enable a0~a17 address input s /oe output enable vcc power ( 2.7~3.3v ) /lb low er byte control (i/o1~i/o8) vss ground /ub upper byte control (i/o9~i/o16) nc no connection memory array 256k x 16 row decoder sense a mp write driver data i/o buffer i/o1 i/o8 i/o9 i/o16 column decoder block decoder pre decoder add input buffer a0 a17 /cs /oe /lb /ub /we 1 2 3 4 5 6 a b c d e f g h fbga /lb io 9 io1 0 /oe a0 a1 a2 nc /ub a3 a 4 /cs io1 io1 1 a 5 a 6 io2 io3 vss io1 2 a 17 a 7 io4 vcc vcc io1 3 nc a16 io5 vss io1 5 io1 4 a 14 a1 5 io 6 io 7 io16 nc a1 2 a1 3 /we io8 nc a 8 a9 a1 0 a1 1 nc
hy62 uf16404d series rev. 04 / oct .01 2 ordering information part no. speed power temp . package hy62uf 1640 4d - d f (i) 55/ 70 ll - part i fbga hy62uf1640 4d - sf (i) 55/ 70 sl - part i fbga note 1. i : industrial absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output voltage - 0. 3 to 3.6 v vcc power supply - 0. 3 to 4. 6 v t a operating temperature - 40 to 85 c hy62uf1640 4 d - i t stg storage temperature - 55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratin gs may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is no t implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table i/o pin /cs /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x x x x h h des elected hi gh - z hi gh - z standby l x l h h x l output disabled hi gh - z hi gh - z active l h d out hi gh - z h l hi gh - z d out l h l l l read d out d out active l h d in hi gh - z h l hi gh - z d in l l x l l write d in d in active note: 1. h=v ih , l=v il , x=don't care ( v il or v ih ) 2. / ub, / lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when / lb is low, data is written or read to the lower byte, i/o 1 - i/o 8. when / ub is low, data is written or read to the upper byte , i/o 9 - i/o 16.
hy62 uf16404d series rev. 04 / oct .01 3 recommended dc operating condition symbol parameter min. typ max. unit vcc supply voltage 2.7 3.0 3. 3 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0. 3 v v il input low voltage - 0. 3 1. - 0. 6 v note : 1. undershoot : vil = - 1.5v for pulse width less than 30ns 2. undershoot is sampled, not 100% tested. dc electrical characteristics t a = - 40 c to 85 c sym parameter test condition min ty p 1. max unit i li input leakage current vss < v in < vcc - 1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il or / ub = v ih , /lb = v ih - 1 - 1 ua icc operating power supply curren t /cs = v il , v in = v ih or v il, i i/o = 0ma 4 ma /cs = v il, v in = v ih or v il, cycle time = min, 100% duty, i i/o = 0ma 40 ma i cc1 average operating current /cs < 0.2v , v in < 0.2v or v in > vcc - 0.2v , cycle time = 1us , 100% duty, i i/o = 0ma 4 ma i sb standby current (ttl input) /cs = v ih or /ub, /lb = v ih v in = v ih or v il 0 .3 ma sl 0.2 6 ua i sb1 standby current (cmos input) /cs > vcc - 0.2v or /ub, /lb > vcc - 0.2v v in > vcc - 0.2v or v in < v ss + 0.2v ll 0.2 12 ua v ol output low i ol = 2.1ma - - 0. 4 v v oh output high i oh = - 1.0ma 2. 4 - - v note 1. typ ical values are at vcc = 3.0v t a = 25 c 2 . typical values are not 100% tested capacitance (temp = 25 c , f= 1.0mhz) symbol parameter condition max. unit c in input capacitance(add, /cs ,/lb,/ub , /we, /oe) v in = 0v 8 pf c out output capacitance(i/o) v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested ac characteristics
hy62 uf16404d series rev. 04 / oct .01 4 t a = - 40 c to 85 c , unless otherwise specified 55 ns 70 ns # symbol parameter min. max. min. max. unit 1 trc read cycle time 55 - 70 - ns 2 taa addre ss access time - 55 - 70 ns 3 tacs chip select access time - 55 - 70 ns 4 toe output enable to output valid - 3 0 - 35 ns 5 tba /lb, /ub access time - 5 5 - 7 0 ns 6 tclz chip select to output in low z 10 - 10 - ns 7 tolz output enable to output in l ow z 5 - 5 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - ns 9 tchz chip deselection to output in high z 0 20 0 30 ns 10 tohz out disable to output in high z 0 20 0 30 ns 11 tbhz /lb, /ub disable to output in high z 0 20 0 30 ns 12 toh outpu t hold from address change 10 - 10 - ns 13 twc write cycle time 55 - 70 - ns 14 tcw chip selection to end of write 50 - 60 - ns 15 taw address valid to end of write 50 - 60 - ns 16 tbw /lb, /ub valid to end of write 50 - 60 - ns 17 tas address set - up time 0 - 0 - ns 18 twp write pulse width 45 - 50 - ns 19 twr write recovery time 0 - 0 - ns 20 twhz write to output in high z 0 20 0 20 ns 21 tdw data to write time overlap 25 - 30 - ns 22 tdh data hold from write time 0 - 0 - ns 23 tow output a ctive from end of write 5 - 5 - ns ac test conditions t a = - 40 c to 85 c , unless otherwise specified p arameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing reference level 1.5v tclz, tolz, t blz, tchz, tohz, tbhz, twhz, tow cl = 5 pf + 1ttl load output load others cl = 3 0pf + 1ttl load ac test loads d out 1728 ohm cl(1) 1029 ohm v tm =2.8v note 1. including jig and scope capacitance: read cycle write cycle
hy62 uf16404d series rev. 04 / oct .01 5 timing diagram read cycle 1 (note 1 , 4 ) read cycle 2 (note 1,2, 4 ) trc taa data valid previous data toh toh addr data out read cycle 3(note 1, 2, 4) /cs /ub, /lb tacs data valid tclz(3) tchz(3) data out notes: 1. a read occurs during the overlap of a low /oe, a high /we, a low / cs and /ub and / or /lb . 2. /oe = v il 3. transition is meas ured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active addr trc / cs taa tacs toh data valid high - z data out / ub ,/ lb / oe tba toe tclz (3) tblz (3) t olz (3) t chz (3) t bhz (3) tohz (3)
hy62 uf16404d series rev. 04 / oct .01 6 write cycle 1 (1,4, 8 ) (/we controlled) write cycle 2 (note 1,4, 8) (/cs controlled) data valid addr data out / cs / ub, / lb / we twc tcw twr (2) tbw taw twp data in high - z tas twhz (3,7) tdw tdh tow (5) (6) data valid addr data out / cs / ub, / lb / we twc tcw twr (2) tbw taw twp data in tdw tdh high - z high - z tas
hy62 uf16404d series rev. 04 / oct .01 7 notes: 1. a write occurs during the overlap of a low /we, a low /cs and a low /ub and/or /lb . 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured + 200mv from steady state. this parameter is sampled and not 100% tested. 8 . /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active data retention electric characteristic t a = - 40 c to 85 c symbol parameter test condition m in typ 1. max unit v dr vcc for data retention /cs > vcc - 0.2v or /ub, /lb > vcc - 0.2v , v in > vcc - 0.2v or v in < v ss + 0.2v 1. 5 - 3.3 v sl - 0.2 3 ua iccdr data retention current vcc= 1.5 v , /cs > vcc - 0.2v or /ub, /lb > vcc - 0.2v v in > vcc - 0.2v or v in < v ss + 0.2v ll - 0. 2 12 ua t cdr chip deselect to data retention time 0 - - ns tr operating recovery time see data retention timing diagram trc - - ns notes: 1. typical values are under the conditi on of t a = 25 c . 2. typical value are sampled and not 100% tested data retention timing diagram / cs vdr / cs > vcc-0.2v tcdr tr vss vcc 2.7v vih data retention mode
hy62 uf16404d series rev. 04 / oct .01 8 package information 48ball fine pitch ball grid array package (f) bottom view top view b a a1 corner index area 6 5 4 3 2 1 a a b c d c c1 e f g c1/2 h b1/2 b1 side view 5 e1 e2 c e seating plane 4 a r 3 d(diameter) symb ol min. typ. max. a - 0.75 - b - 3.75 - b1 5.9 6.0 6.1 c - 5.25 - c1 7.9 8.0 8.1 d 0.3 0.35 0.4 e 0.9 1.0 1.10 e1 - 0.75 - e2 0.20 0.25 0.30 r - - 0. 08 note 1. dimensioning and tolerancing per asme y14. 5 m - 1994. 2. all dimensions are millimeters. 3. dimension ?d? is me asured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5. this is a controlling dimension.
hy62 uf16404d series rev. 04 / oct .01 9 marking information package marking example h y u f 6 4 0 4 d c s s t y w w p x x x x x k o r fbga index ? hyuf6404d : part name ? c : power consumption - d : low low power - s : super low power ? ss : speed - 55 : 55ns - 70 : 70ns ? t : temperature - i : industrial ( - 40 ~ 85 c ) ? y : year (ex : 0 = year 2000, 1= year 2001) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item package marking example h y u f 6 4 0 4 d c s s t y w w p x x x x x k o r fbga index ? hyuf6404d : part name ? c : power consumption - d : low low power - s : super low power ? ss : speed - 55 : 55ns - 70 : 70ns ? t : temperature - i : industrial ( - 40 ~ 85 c ) ? y : year (ex : 0 = year 2000, 1= year 2001) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item
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